ADC Successive Approximation Register (ADC_SAR)

Überblick

General Description

Symbol Diagram

The ADC Successive Approximation Register (ADC_SAR) component provides medium-speed (maximum 1-msps sampling), medium-resolution (12 bits maximum), analog-to-digital conversion.

Features

  • Supports PSoC™ 5LP family of devices
  • 12-bit resolution at up to 1 msps maximum
  • Four power modes
  • Selectable resolution and sample rate
  • Single-ended or differential input
Support