SRAM (Static RAM)
Industry's broadest portfolio of low-power and high-speed SRAM with densities ranging from 256 Kb to 144 Mb with stable supply and long-term support
SRAM (Static RAM) Unterkategorien
Alle Unterkategorien schließen Alle Unterkategorien anzeigenInfineon's stand-alone SRAM is a random-access memory that offers you an easy way to add more RAM to your applications. Infineon offers a wide variety of High-speed, Low-power and reliable SRAMs for a broad variety of applications such as Networking, Automotive, Consumer electronics, Industrial, Medical, Aerospace and Defense. With a diversified portfolio of Asynchronous, Synchronous and Dual-port SRAMs and a commitment of stable supply and long-term product support, Infineon is a preferred SRAM supplier. These devices are available in densities ranging from 256 Kbit to 64 Mbit with on-chip ECC. Infineon also supports high-reliability, radiation tolerant products for mission critical applications.
About
SRAM uses flip-flop based latching circuitry to store each bit. Nearly all SRAM either use a 4-transistor or a 6-transistor memory cell. These cell structures allow data to be stored for an indefinite amount of time in the device if it is powered.
Infineon's standalone SRAM is a random-access memory that offers you an easy way to add more RAM to your applications. Infineon offers a wide variety of high-speed, low-power, and reliable SRAM for a broad variety of applications such as networking, automotive, consumer electronics, industrial, medical, aerospace, and defense. With a diversified portfolio of asynchronous and synchronous SRAM and a commitment to stable supply and long-term product support, Infineon is a preferred SRAM supplier. These devices are available in densities ranging from 256 Kb to 64 Mb with on-chip ECC.
SRAM come in two different flavors based on synchronisation with the clock:
- Synchronous SRAM are synchronized with an external clock signal
- Asynchronous SRAM do not depend on the state of the clock signal
Asynchronous SRAM
Infineon's asynchronous SRAM memory products are available in densities ranging from 256 Kb to 64 Mb and classified into two families based on their access times:
Low-power asynchronous SRAM: These are devices that typically operate in the 45 ns and slower speed range. These SRAMs are typically designed to consume very low power and are used in applications where power is a major concern. They are often used for temporary data storage and scratchpad applications. Infineon’s MOBL™ micropower asynchronous SRAM belong to this family.
Fast asynchronous SRAM: These are devices that typically operate in the sub-25 ns region. They are often used in buffer and cache memory applications. Infineon offers Fast SRAM with PowerSnooze to offer devices that combine the access time of fast asynchronous SRAM with a unique ultra-low-power sleep mode Read more about asynchronous SRAM here
Synchronous SRAM
Synchronous SRAM memory products are available in densities ranging from 9 Mb to 144 Mb and are classified based on the data transfer rates:
Single data rate SRAM: These are synchronous SRAM, where one word of data is transferred between the SRAM and controller in a given clock cycle. These include Infineon’s pipelined SRAM, flowthrough SRAM, burst SRAM, and network SRAM – NoBL™/ZBT™ SRAM.
Double and quad data rate SRAM: These SRAMs can transfer multiple data words in a given cycle and are designed to be the SRAMs of choice for networking applications and data storage applications that provide up to 80 Gbps data transfer rate. DDR-II and DDR-II+ transfer data on both the rising and falling clock edges using a common data bus interface. QDR-II and QDR-II+ utilize two separate dedicated double-data-rate bus interfaces. Read more about synchronous SRAM here
Error correction code - lowest soft error rate <0.1 FIT/Mbit
With on-chip hardware ECC (error correction code), Infineon’s SRAM perform all ECC-related functions inline without intervention. Higher-energy extraterrestrial radiation can flip multiple adjacent bits, leading to multi-bit errors. The single-bit error detection and correction capability of ECC is supplemented by a bit-interleaving scheme to prevent the occurrence of multi-bit errors. Together, these features provide a significant improvement in soft error rate (SER) performance, resulting in industry-leading FIT rates of less than 0.1 FIT/Mb.
SRAM vs competing memory devices
SRAM don’t require periodic refresh like DRAM, hence offering better performance. In the case of DRAM, data is stored in the capacitor as an electrical charge, but this charge leaks over time and leads to data loss. Therefore, DRAM must be refreshed periodically to preserve the stored data. This negatively impacts DRAM performance and power dissipation.
Hence, SRAM are also typically faster and have lower power consumption than DRAM.
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