S70KL1281DABHI023 High-Performance 128 MBit HYPERRAM with 40ns Initial Access Time and 200 MByte/s Interface Bandwidth
Overview
The Cypress® HyperRAM™ device is a high-speed CMOS DRAM with a HyperBus interface. The 128 Mb version is a dual-die stack of 64 Mb devices. With refresh control logic, it resembles PSRAM to the host, eliminating the need for manual refresh operations. The host should manage transaction duration to accommodate internal refresh needs.
Summary of Features
- 3.0 V I/O, 11 bus signals:Single ended clock (CK)
- 1.8 V I/O, 12 bus signals: Differential clock (CK, CK#)
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Read-Write Data Strobe (RWDS)
- RWDS DCARS Timing
- Double-Data Rate (DDR)
- 100 MHz clock rate (200 MBps) at 3.0 V VCC
- Sequential burst transactions
- Configurable Burst Characteristics
Support
