48 #ifndef TLE94x1_DEFINES_H 49 #define TLE94x1_DEFINES_H 67 #define SBC_M_S_CTRL (0b00000001U) 74 #define SBC_HW_CTRL_0 (0b00000010U) 81 #define SBC_WD_CTRL (0b00000011U) 88 #define SBC_BUS_CTRL_0 (0b00000100U) 95 #define SBC_WK_CTRL_0 (0b00000110U) 102 #define SBC_WK_CTRL_1 (0b00000111U) 109 #define SBC_WK_PUPD_CTRL (0b00001000U) 116 #define SBC_BUS_CTRL_3 (0b00001011U) 123 #define SBC_TIMER_CTRL (0b00001100U) 130 #define SBC_HW_CTRL_1 (0b00001110U) 137 #define SBC_HW_CTRL_2 (0b00001111U) 144 #define SBC_GPIO_CTRL (0b00010111U) 151 #define SBC_PWM_CTRL (0b00011000U) 158 #define SBC_PWM_FREQ_CTRL (0b00011100U) 165 #define SBC_HW_CTRL_3 (0b00011101U) 172 #define SBC_SYS_STATUS_CTRL_0 (0b00011110U) 179 #define SBC_SYS_STATUS_CTRL_1 (0b00011111U) 197 #define SBC_SWK_CTRL (0b00100000U) 204 #define SBC_SWK_BTL0_CTRL (0b00100001U) 211 #define SBC_SWK_BTL1_CTRL (0b00100010U) 218 #define SBC_SWK_ID3_CTRL (0b00100011U) 225 #define SBC_SWK_ID2_CTRL (0b00100100U) 232 #define SBC_SWK_ID1_CTRL (0b00100101U) 239 #define SBC_SWK_ID0_CTRL (0b00100110U) 246 #define SBC_SWK_MASK_ID3_CTRL (0b00100111U) 253 #define SBC_SWK_MASK_ID2_CTRL (0b00101000U) 260 #define SBC_SWK_MASK_ID1_CTRL (0b00101001U) 267 #define SBC_SWK_MASK_ID0_CTRL (0b00101010U) 274 #define SBC_SWK_DLC_CTRL (0b00101011U) 281 #define SBC_SWK_DATA7_CTRL (0b00101100U) 288 #define SBC_SWK_DATA6_CTRL (0b00101101U) 295 #define SBC_SWK_DATA5_CTRL (0b00101110U) 302 #define SBC_SWK_DATA4_CTRL (0b00101111U) 309 #define SBC_SWK_DATA3_CTRL (0b00110000U) 316 #define SBC_SWK_DATA2_CTRL (0b00110001U) 323 #define SBC_SWK_DATA1_CTRL (0b00110010U) 330 #define SBC_SWK_DATA0_CTRL (0b00110011U) 337 #define SBC_SWK_CAN_FD_CTRL (0b00110100U) 344 #define SBC_SWK_OSC_TRIM_CTRL (0b00111000U) 351 #define SBC_SWK_OPT_CTRL (0b00111001U) 358 #define SBC_SWK_OSC_CAL_H_STAT (0b00111010U) 365 #define SBC_SWK_OSC_CAL_L_STAT (0b00111011U) 372 #define SBC_SWK_CDR_CTRL1 (0b00111100U) 379 #define SBC_SWK_CDR_CTRL2 (0b00111101U) 386 #define SBC_SWK_CDR_LIMIT_HIGH_CTRL (0b00111110U) 393 #define SBC_SWK_CDR_LIMIT_LOW_CTRL (0b00111111U) 412 #define SBC_SUP_STAT_1 (0b01000000U) 419 #define SBC_SUP_STAT_0 (0b01000001U) 426 #define SBC_THERM_STAT (0b01000010U) 433 #define SBC_DEV_STAT (0b01000011U) 440 #define SBC_BUS_STAT (0b01000100U) 447 #define SBC_WK_STAT_0 (0b01000110U) 454 #define SBC_WK_STAT_1 (0b01000111U) 461 #define SBC_WK_LVL_STAT (0b01001000U) 468 #define SBC_GPIO_OC_STAT (0b01010100U) 475 #define SBC_GPIO_OL_STAT (0b01010101U) 494 #define SBC_SWK_STAT (0b01110000U) 501 #define SBC_SWK_ECNT_STAT (0b01110001U) 508 #define SBC_SWK_CDR_STAT1 (0b01110010U) 515 #define SBC_SWK_CDR_STAT2 (0b01110011U) 522 #define SBC_FAM_PROD_STAT (0b01111110U) 542 #define SBC_M_S_CTRL_MODE_Pos (6U) 548 #define SBC_M_S_CTRL_MODE_Msk (0b11000000U) 554 #define SBC_M_S_CTRL_VCC2_ON_Pos (3U) 560 #define SBC_M_S_CTRL_VCC2_ON_Msk (0b00011000U) 566 #define SBC_M_S_CTRL_VCC1_OV_RST_Pos (2U) 572 #define SBC_M_S_CTRL_VCC1_OV_RST_Msk (0b00000100U) 578 #define SBC_M_S_CTRL_VCC1_RT_Pos (0U) 584 #define SBC_M_S_CTRL_VCC1_RT_Msk (0b00000011U) 595 #define SBC_HW_CTRL_0_SOFT_RESET_RST_Pos (6U) 602 #define SBC_HW_CTRL_0_SOFT_RESET_RST_Msk (0b01000000U) 609 #define SBC_HW_CTRL_0_FO_ON_Pos (5U) 616 #define SBC_HW_CTRL_0_FO_ON_Msk (0b00100000U) 623 #define SBC_HW_CTRL_0_CP_EN_Pos (2U) 630 #define SBC_HW_CTRL_0_CP_EN_Msk (0b00000100U) 637 #define SBC_HW_CTRL_0_CFG1_Pos (0U) 644 #define SBC_HW_CTRL_0_CFG1_Msk (0b00000001U) 655 #define SBC_WD_CTRL_CHECKSUM_Pos (7U) 662 #define SBC_WD_CTRL_CHECKSUM_Msk (0b10000000U) 669 #define SBC_WD_CTRL_WD_STM_EN_0_Pos (6U) 676 #define SBC_WD_CTRL_WD_STM_EN_0_Msk (0b01000000U) 683 #define SBC_WD_CTRL_WD_WIN_Pos (5U) 690 #define SBC_WD_CTRL_WD_WIN_Msk (0b00100000U) 697 #define SBC_WD_CTRL_WD_EN_WK_BUS_Pos (4U) 704 #define SBC_WD_CTRL_WD_EN_WK_BUS_Msk (0b00010000U) 711 #define SBC_WD_CTRL_WD_TIMER_Pos (0U) 718 #define SBC_WD_CTRL_WD_TIMER_Msk (0b00000111U) 728 #define SBC_BUS_CTRL_0_CAN_Pos (0U) 735 #define SBC_BUS_CTRL_0_CAN_Msk (0b00000111U) 745 #define SBC_WK_CTRL_0_TIMER_WK_EN_Pos (6U) 752 #define SBC_WK_CTRL_0_TIMER_WK_EN_Msk (0b01000000U) 759 #define SBC_WK_CTRL_0_WD_STM_EN_1_Pos (2U) 766 #define SBC_WK_CTRL_0_WD_STM_EN_1_Msk (0b00000100U) 777 #define SBC_WK_CTRL_1_INT_GLOBAL_Pos (7U) 784 #define SBC_WK_CTRL_1_INT_GLOBAL_Msk (0b10000000U) 791 #define SBC_WK_CTRL_1_WK_MEAS_Pos (5U) 798 #define SBC_WK_CTRL_1_WK_MEAS_Msk (0b00100000U) 805 #define SBC_WK_CTRL_1_WK_EN_Pos (0U) 812 #define SBC_WK_CTRL_1_WK_EN_Msk (0b00000001U) 823 #define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos (6U) 830 #define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk (0b11000000U) 837 #define SBC_WK_PUPD_CTRL_WK_PUPD_Pos (0U) 844 #define SBC_WK_PUPD_CTRL_WK_PUPD_Msk (0b00000011U) 854 #define SBC_BUS_CTRL_3_CAN_FLASH_Pos (4U) 861 #define SBC_BUS_CTRL_3_CAN_FLASH_Msk (0b00010000U) 872 #define SBC_TIMER_CTRL_TIMER_ON_Pos (4U) 879 #define SBC_TIMER_CTRL_TIMER_ON_Msk (0b01110000U) 886 #define SBC_TIMER_CTRL_TIMER_PER_Pos (0U) 893 #define SBC_TIMER_CTRL_TIMER_PER_Msk (0b00001111U) 904 #define SBC_HW_CTRL_1_RSTN_HYS_Pos (7U) 911 #define SBC_HW_CTRL_1_RSTN_HYS_Msk (0b10000000U) 918 #define SBC_HW_CTRL_1_TSD2_DEL_Pos (5U) 925 #define SBC_HW_CTRL_1_TSD2_DEL_Msk (0b00100000U) 932 #define SBC_HW_CTRL_1_RSTN_DEL_Pos (4U) 939 #define SBC_HW_CTRL_1_RSTN_DEL_Msk (0b00010000U) 946 #define SBC_HW_CTRL_1_CFG_LOCK_0_Pos (3U) 953 #define SBC_HW_CTRL_1_CFG_LOCK_0_Msk (0b00001000U) 964 #define SBC_HW_CTRL_2_2MHZ_FREQ_Pos (5U) 971 #define SBC_HW_CTRL_2_2MHZ_FREQ_Msk (0b11100000U) 978 #define SBC_HW_CTRL_2_I_PEAK_TH_Pos (4U) 985 #define SBC_HW_CTRL_2_I_PEAK_TH_Msk (0b00010000U) 992 #define SBC_HW_CTRL_2_SS_MOD_FR_Pos (2U) 999 #define SBC_HW_CTRL_2_SS_MOD_FR_Msk (0b00001100U) 1006 #define SBC_HW_CTRL_2_CFG_LOCK_1_Pos (0U) 1013 #define SBC_HW_CTRL_2_CFG_LOCK_1_Msk (0b00000001U) 1023 #define SBC_GPIO_CTRL_GPIO_Pos (0U) 1030 #define SBC_GPIO_CTRL_GPIO_Msk (0b00000111U) 1040 #define SBC_PWM_CTRL_PWM_DC_Pos (0U) 1047 #define SBC_PWM_CTRL_PWM_DC_Msk (0b11111111U) 1057 #define SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos (0U) 1065 #define SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk (0b00000011U) 1076 #define SBC_HW_CTRL_3_TSD_THR_Pos (2U) 1083 #define SBC_HW_CTRL_3_TSD_THR_Msk (0b00000100U) 1090 #define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos (0U) 1097 #define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk (0b00000011U) 1107 #define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos (0U) 1114 #define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk (0b11111111U) 1125 #define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos (0U) 1132 #define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk (0b11111111U) 1153 #define SBC_SWK_CTRL_OSC_CAL_Pos (7U) 1160 #define SBC_SWK_CTRL_OSC_CAL_Msk (0b10000000U) 1167 #define SBC_SWK_CTRL_TRIM_EN_Pos (5U) 1174 #define SBC_SWK_CTRL_TRIM_EN_Msk (0b01100000U) 1181 #define SBC_SWK_CTRL_CANTO_MASK_Pos (4U) 1188 #define SBC_SWK_CTRL_CANTO_MASK_Msk (0b00010000U) 1195 #define SBC_SWK_CTRL_CFG_VAL_Pos (0U) 1202 #define SBC_SWK_CTRL_CFG_VAL_Msk (0b00000001U) 1213 #define SBC_SWK_BTL0_CTRL_TBIT_Pos (0U) 1220 #define SBC_SWK_BTL0_CTRL_TBIT_Msk (0b11111111U) 1231 #define SBC_SWK_BTL1_CTRL_SP_Pos (0U) 1238 #define SBC_SWK_BTL1_CTRL_SP_Msk (0b00111111U) 1249 #define SBC_SWK_ID3_CTRL_ID28_21_Pos (0U) 1256 #define SBC_SWK_ID3_CTRL_ID28_21_Msk (0b11111111U) 1267 #define SBC_SWK_ID2_CTRL_ID20_13_Pos (0U) 1274 #define SBC_SWK_ID2_CTRL_ID20_13_Msk (0b11111111U) 1285 #define SBC_SWK_ID1_CTRL_ID12_5_Pos (0U) 1292 #define SBC_SWK_ID1_CTRL_ID12_5_Msk (0b11111111U) 1303 #define SBC_SWK_ID0_CTRL_ID4_0_Pos (2U) 1310 #define SBC_SWK_ID0_CTRL_ID4_0_Msk (0b01111100U) 1317 #define SBC_SWK_ID0_CTRL_RTR_Pos (1U) 1324 #define SBC_SWK_ID0_CTRL_RTR_Msk (0b00000010U) 1331 #define SBC_SWK_ID0_CTRL_IDE_Pos (0U) 1338 #define SBC_SWK_ID0_CTRL_IDE_Msk (0b00000001U) 1349 #define SBC_SWK_MASK_ID3_CTRL_Pos (0U) 1356 #define SBC_SWK_MASK_ID3_CTRL_Msk (0b11111111U) 1367 #define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos (0U) 1374 #define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk (0b11111111U) 1385 #define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos (0U) 1392 #define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk (0b11111111U) 1403 #define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos (2U) 1410 #define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk (0b01111100U) 1421 #define SBC_SWK_DLC_CTRL_DLC_Pos (0U) 1428 #define SBC_SWK_DLC_CTRL_DLC_Msk (0b00001111U) 1439 #define SBC_SWK_DATA7_CTRL_Pos (0U) 1446 #define SBC_SWK_DATA7_CTRL_Msk (0b11111111U) 1457 #define SBC_SWK_DATA6_CTRL_Pos (0U) 1464 #define SBC_SWK_DATA6_CTRL_Msk (0b11111111U) 1475 #define SBC_SWK_DATA5_CTRL_Pos (0U) 1482 #define SBC_SWK_DATA5_CTRL_Msk (0b11111111U) 1493 #define SBC_SWK_DATA4_CTRL_Pos (0U) 1500 #define SBC_SWK_DATA4_CTRL_Msk (0b11111111U) 1511 #define SBC_SWK_DATA3_CTRL_Pos (0U) 1518 #define SBC_SWK_DATA3_CTRL_Msk (0b11111111U) 1529 #define SBC_SWK_DATA2_CTRL_Pos (0U) 1536 #define SBC_SWK_DATA2_CTRL_Msk (0b11111111U) 1547 #define SBC_SWK_DATA1_CTRL_Pos (0U) 1554 #define SBC_SWK_DATA1_CTRL_Msk (0b11111111U) 1565 #define SBC_SWK_DATA0_CTRL_Pos (0U) 1572 #define SBC_SWK_DATA0_CTRL_Msk (0b11111111U) 1583 #define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos (5U) 1590 #define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk (0b00100000U) 1597 #define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos (4U) 1604 #define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk (0b00010000U) 1611 #define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos (1U) 1618 #define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk (0b00001110U) 1625 #define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos (0U) 1632 #define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk (0b00000001U) 1643 #define SBC_SWK_OSC_TRIM_CTRL_Pos (0U) 1650 #define SBC_SWK_OSC_TRIM_CTRL_Msk (0b01111111U) 1661 #define SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos (7U) 1668 #define SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk (0b10000000U) 1679 #define SBC_SWK_OSC_CAL_H_STAT_Pos (0U) 1686 #define SBC_SWK_OSC_CAL_H_STAT_Msk (0b11111111U) 1697 #define SBC_SWK_OPT_CAL_L_STAT_Pos (0U) 1704 #define SBC_SWK_OPT_CAL_L_STAT_Msk (0b11111111U) 1715 #define SBC_SWK_CDR_CTRL1_SEL_FILT_Pos (2U) 1722 #define SBC_SWK_CDR_CTRL1_SEL_FILT_Msk (0b00001100U) 1729 #define SBC_SWK_CDR_CTRL1_CDR_EN_Pos (0U) 1736 #define SBC_SWK_CDR_CTRL1_CDR_EN_Msk (0b00000001U) 1747 #define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos (0U) 1754 #define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk (0b00000011U) 1765 #define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos (0U) 1772 #define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk (0b11111111U) 1783 #define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos (0U) 1790 #define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk (0b11111111U) 1811 #define SBC_SUP_STAT_1_VS_UV_Pos (6U) 1818 #define SBC_SUP_STAT_1_VS_UV_Msk (0b01000000U) 1825 #define SBC_SUP_STAT_1_VS_OV_Pos (5U) 1832 #define SBC_SUP_STAT_1_VS_OV_Msk (0b00100000U) 1839 #define SBC_SUP_STAT_1_VCC1_OV_Pos (1U) 1846 #define SBC_SUP_STAT_1_VCC1_OV_Msk (0b00000010U) 1853 #define SBC_SUP_STAT_1_VCC1_WARN_Pos (0U) 1860 #define SBC_SUP_STAT_1_VCC1_WARN_Msk (0b00000001U) 1871 #define SBC_SUP_STAT_0_POR_Pos (7U) 1878 #define SBC_SUP_STAT_0_POR_Msk (0b10000000U) 1885 #define SBC_SUP_STAT_0_VCC2_OT_Pos (4U) 1892 #define SBC_SUP_STAT_0_VCC2_OT_Msk (0b00010000U) 1899 #define SBC_SUP_STAT_0_VCC2_UV_Pos (3U) 1906 #define SBC_SUP_STAT_0_VCC2_UV_Msk (0b00001000U) 1913 #define SBC_SUP_STAT_0_VCC1_SC_Pos (2U) 1920 #define SBC_SUP_STAT_0_VCC1_SC_Msk (0b00000100U) 1927 #define SBC_SUP_STAT_0_VCC1_UV_Pos (0U) 1934 #define SBC_SUP_STAT_0_VCC1_UV_Msk (0b00000001U) 1945 #define SBC_THERM_STAT_TSD2_SAFE_Pos (3U) 1952 #define SBC_THERM_STAT_TSD2_SAFE_Msk (0b00001000U) 1959 #define SBC_THERM_STAT_TSD2_Pos (2U) 1966 #define SBC_THERM_STAT_TSD2_Msk (0b00000100U) 1973 #define SBC_THERM_STAT_TSD1_Pos (1U) 1980 #define SBC_THERM_STAT_TSD1_Msk (0b00000010U) 1987 #define SBC_THERM_STAT_TPW_Pos (0U) 1994 #define SBC_THERM_STAT_TPW_Msk (0b00000001U) 2005 #define SBC_DEV_STAT_DEV_STAT_Pos (6U) 2012 #define SBC_DEV_STAT_DEV_STAT_Msk (0b11000000U) 2019 #define SBC_DEV_STAT_WD_FAIL_Pos (2U) 2026 #define SBC_DEV_STAT_WD_FAIL_Msk (0b00001100U) 2033 #define SBC_DEV_STAT_SPI_FAIL_Pos (1U) 2040 #define SBC_DEV_STAT_SPI_FAIL_Msk (0b00000010U) 2047 #define SBC_DEV_STAT_FAILURE_Pos (0U) 2054 #define SBC_DEV_STAT_FAILURE_Msk (0b00000001U) 2065 #define SBC_BUS_STAT_CANTO_Pos (4U) 2072 #define SBC_BUS_STAT_CANTO_Msk (0b00010000U) 2079 #define SBC_BUS_STAT_SYSERR_Pos (3U) 2086 #define SBC_BUS_STAT_SYSERR_Msk (0b00001000U) 2093 #define SBC_BUS_STAT_CAN_FAIL_Pos (1U) 2100 #define SBC_BUS_STAT_CAN_FAIL_Msk (0b00000110U) 2107 #define SBC_BUS_STAT_VCAN_UV_Pos (0U) 2114 #define SBC_BUS_STAT_VCAN_UV_Msk (0b00000001U) 2125 #define SBC_WK_STAT_0_CAN_WU_Pos (5U) 2132 #define SBC_WK_STAT_0_CAN_WU_Msk (0b00100000U) 2139 #define SBC_WK_STAT_0_TIMER_WU_Pos (4U) 2146 #define SBC_WK_STAT_0_TIMER_WU_Msk (0b00010000U) 2153 #define SBC_WK_STAT_0_WK_WU_Pos (0U) 2160 #define SBC_WK_STAT_0_WK_WU_Msk (0b00000001U) 2171 #define SBC_WK_STAT_1_GPIO_WK_WU_Pos (4U) 2178 #define SBC_WK_STAT_1_GPIO_WK_WU_Msk (0b00010000U) 2189 #define SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos (7U) 2196 #define SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk (0b10000000U) 2203 #define SBC_WK_LVL_STAT_CFG0_STATE_Pos (6U) 2210 #define SBC_WK_LVL_STAT_CFG0_STATE_Msk (0b01000000U) 2217 #define SBC_WK_LVL_STAT_GPIO_LVL_Pos (4U) 2224 #define SBC_WK_LVL_STAT_GPIO_LVL_Msk (0b00010000U) 2231 #define SBC_WK_LVL_STAT_WK_LVL_Pos (0U) 2238 #define SBC_WK_LVL_STAT_WK_LVL_Msk (0b00000001U) 2249 #define SBC_GPIO_OC_STAT_GPIO_OC_Pos (6U) 2256 #define SBC_GPIO_OC_STAT_GPIO_OC_Msk (0b01000000U) 2267 #define SBC_GPIO_OL_STAT_GPIO_OL_Pos (6U) 2274 #define SBC_GPIO_OL_STAT_GPIO_OL_Msk (0b01000000U) 2297 #define SBC_SWK_STAT_SYNC_Pos (6U) 2304 #define SBC_SWK_STAT_SYNC_Msk (0b01000000U) 2311 #define SBC_SWK_STAT_CANSIL_Pos (3U) 2318 #define SBC_SWK_STAT_CANSIL_Msk (0b00001000U) 2325 #define SBC_SWK_STAT_SWK_SET_Pos (2U) 2332 #define SBC_SWK_STAT_SWK_SET_Msk (0b00000100U) 2339 #define SBC_SWK_STAT_WUP_Pos (1U) 2346 #define SBC_SWK_STAT_WUP_Msk (0b00000010U) 2353 #define SBC_SWK_STAT_WUF_Pos (0U) 2360 #define SBC_SWK_STAT_WUF_Msk (0b00000001U) 2374 #define SBC_SWK_ECNT_STAT_ECNT_Pos (0U) 2381 #define SBC_SWK_ECNT_STAT_ECNT_Msk (0b00111111U) 2392 #define SBC_SWK_CDR_STAT1_NAVG_SAT_Pos (0U) 2399 #define SBC_SWK_CDR_STAT1_NAVG_SAT_Msk (0b11111111U) 2410 #define SBC_SWK_CDR_STAT2_NAVG_SAT_Pos (4U) 2417 #define SBC_SWK_CDR_STAT2_NAVG_SAT_Msk (0b11110000U) 2438 #define SBC_FAM_PROD_STAT_FAM_Pos (4U) 2445 #define SBC_FAM_PROD_STAT_FAM_Msk (0b11110000U) 2452 #define SBC_FAM_PROD_STAT_PROD_Pos (0U) 2459 #define SBC_FAM_PROD_STAT_PROD_Msk (0b00001111U) 2476 SBC_MODE_NORMAL = 0x00U,
2484 SBC_VCC2_OFF = 0x00U,
2486 SBC_VCC2_ON_NORMAL_STOP,
2492 SBC_VCC1_OV_RST_NOACTION = 0x00U,
2493 SBC_VCC1_OV_RST_RESTART_FAILSAFE
2498 SBC_VCC1_RT_VRT1 = 0x00U,
2509 SBC_SOFT_RESET_RST_TRIGGER_SOFTRST = 0x00U,
2510 SBC_SOFT_RESET_RST_NOTRIGGER_SOFTRST
2515 SBC_FO_ON_NOT_ACTIVE = 0x00U,
2521 SBC_CP_EN_OFF = 0x00U,
2527 SBC_CFG1_RESTART_FAILSAFE_2WDFAIL = 0x00U,
2528 SBC_CFG1_RESTART_FAILSAFE_1WDFAIL
2536 SBC_CHECKSUM_0 = 0x00U,
2542 SBC_WD_STM_EN_0_ACTIVE_STOPMODE = 0x00U,
2543 SBC_WD_STM_EN_0_NOTACTIVE_STOPMODE
2548 SBC_WD_WIN_TIMEOUT_WD = 0x00U,
2549 SBC_WD_WIN_WINDOW_WD
2554 SBC_WD_EN_WK_BUS_NOSTART_AFTER_CANWAKE = 0x00U,
2555 SBC_WD_EN_WK_BUS_START_LONGOPENWINDOW_CANWAKE
2560 SBC_WD_TIMER_10MS = 0x00U,
2566 SBC_WD_TIMER_1000MS,
2567 SBC_WD_TIMER_10000MS
2575 SBC_BUS_CTRL_0_CAN_WAKECAPABLE_NOSWK = 0x01U,
2576 SBC_BUS_CTRL_0_CAN_RECEIVEONLY_NOSWK,
2577 SBC_BUS_CTRL_0_CAN_NORMAL_NOSWK,
2578 SBC_BUS_CTRL_0_CAN_OFF,
2579 SBC_BUS_CTRL_0_CAN_WAKECAPABLE_SWK,
2580 SBC_BUS_CTRL_0_CAN_RECEIVEONLY_SWK,
2581 SBC_BUS_CTRL_0_CAN_NORMAL_SWK
2589 WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED = 0x00U,
2590 WK_CTRL_0_TIMER_WK_EN_WAKESOURCE
2595 SBC_WD_STM_EN_1_WATCHDOG_STOPMPDE = 0x00U,
2596 SBC_WD_STM_EN_1_NOWATCHDOG_STOPMODE
2604 SBC_INT_GLOBAL_WAKESOURCES_ONLY = 0x00U,
2605 SBC_INT_GLOBAL_ALLINFORMATIONBITS
2610 SBC_WK_MEAS_WK_AS_WAKEUP = 0x00U,
2611 SBC_WK_MEAS_WK_AS_VOLTAGESENSING
2616 SBC_WK_EN_WAKEUP_DISABLED = 0x00U,
2617 SBC_WK_EN_WAKEUP_ENABLED
2625 SBC_GPIO_WK_PUPD_NOPULLING = 0x00U,
2626 SBC_GPIO_WK_PUPD_PULLDOWN,
2627 SBC_GPIO_WK_PUPD_PULLUP,
2628 SBC_GPIO_WK_PUPD_AUTOMATIC_PULLING
2633 SBC_WK_PUPD_NOPULLING = 0x00U,
2634 SBC_WK_PUPD_PULLDOWN,
2636 SBC_WK_PUPD_AUTOMATIC_PULLING
2644 SBC_CAN_FLASH_DISABLED = 0x00U,
2645 SBC_CAN_FLASH_ENABLED
2653 SBC_TIMER_ON_TIMEROFF_HSX_LOW = 0x00U,
2659 SBC_TIMER_ON_TIMEROFF_HSX_HIGH
2664 SBC_TIMER_PER_10MS = 0x00U,
2667 SBC_TIMER_PER_100MS,
2668 SBC_TIMER_PER_200MS,
2669 SBC_TIMER_PER_500MS,
2687 SBC_RSTN_HYS_DEFAULT = 0x00U,
2688 SBC_RSTN_HYS_HIGHEST_VRT
2693 SBC_TSD2_DEL_NO_WAIT_RELEASE_EXTENSION = 0x00U,
2694 SBC_TSD2_DEL_64S_AFTER_16_TSD2_EVENTS
2699 SBC_RSTN_DEL_TRD1 = 0x00U,
2705 SBC_CFG_LOCK_0_NOTLOCKED = 0x00U,
2706 SBC_CFG_LOCK_0_LOCKED
2714 SBC_2MHZ_FREQ_1_8_MHZ = 0x00U,
2715 SBC_2MHZ_FREQ_2_0_MHZ,
2716 SBC_2MHZ_FREQ_2_2_MHZ,
2717 SBC_2MHZ_FREQ_2_4_MHZ
2722 SBC_I_PEAK_TH_LOW = 0x00U,
2728 SBC_SS_MOD_FR_DISABLED = 0x00U,
2729 SBC_SS_MOD_FR_15_6KHZ,
2730 SBC_SS_MOD_FR_31_2KHZ,
2731 SBC_SS_MOD_FR_62_5KHZ
2736 SBC_CFG_LOCK_1_NOTLOCKED = 0x00U,
2737 SBC_CFG_LOCK_1_LOCKED
2745 SBC_GPIO_FO = 0x00U,
2746 SBC_GPIO_HSS_TIMER = 0x03U,
2748 SBC_GPIO_WAKE_INPUT,
2758 SBC_PWM_DC_0 = 0x00U,
2759 SBC_PWM_DC_10 = 0x19U,
2760 SBC_PWM_DC_20 = 0x51U,
2761 SBC_PWM_DC_30 = 0x4DU,
2762 SBC_PWM_DC_40 = 0x66U,
2763 SBC_PWM_DC_50 = 0x80U,
2764 SBC_PWM_DC_60 = 0x99U,
2765 SBC_PWM_DC_70 = 0xB3U,
2766 SBC_PWM_DC_80 = 0xCCU,
2767 SBC_PWM_DC_90 = 0xE6U,
2768 SBC_PWM_DC_100 = 0xFFU
2776 SBC_PWM_FREQ_100HZ = 0x00U,
2787 SBC_TSD_THR_DEFAULT = 0x00U,
2793 SBC_ICC1_LIM_ADJ_750MA = 0x00U,
2794 SBC_ICC1_LIM_ADJ_1000MA,
2795 SBC_ICC1_LIM_ADJ_1200MA,
2796 SBC_ICC1_LIM_ADJ_1500MA
2814 SBC_OSC_CAL_DISABLED = 0x00U,
2820 SBC_TRIM_EN_LOCKED = 0x00U,
2821 SBC_TRIM_EN_UNLOCKED = 0x03U
2826 SBC_CANTO_MASK_NOINT = 0x00U,
2827 SBC_CANTO_MASK_INT_ON_TO
2832 SBC_CFG_VAL_NOTVALID = 0x00U,
2841 SBC_RTR_NORMAL_DATA_FRAME = 0x00U,
2842 SBC_RTR_REMOTE_TRANSMIT_REQUEST
2847 SBC_IDE_STANDARD = 0x00U,
2856 SBC_DLC_0BYTES = 0x00U,
2872 SBC_DIS_ERR_CNT_ENABLED = 0x00U,
2873 SBC_DIS_ERR_CNT_DISABLED
2878 SBC_RX_FILT_BYP_NOTBYPASSED = 0x00U,
2879 SBC_RX_FILT_BYP_BYPASSED
2884 SBC_FD_FILTER_50NS = 0x00U,
2885 SBC_FD_FILTER_100NS,
2886 SBC_FD_FILTER_150NS,
2887 SBC_FD_FILTER_200NS,
2888 SBC_FD_FILTER_250NS,
2889 SBC_FD_FILTER_300NS,
2890 SBC_FD_FILTER_350NS,
2896 SBC_CAN_FD_EN_DISABLED = 0x00U,
2897 SBC_CAN_FD_EN_ENABLED
2905 SBC_RX_WK_SEL_LOWPOWER = 0x00U,
2906 SBC_RX_WK_SEL_STANDARD
2914 SBC_SEL_FILT_TC8 = 0x00U,
2922 SBC_CDR_EN_DISABLED = 0x00U,
2931 SBC_SEL_OSC_CLK_80MHZ = 0x00U,
2932 SBC_SEL_OSC_CLK_40MHZ,
2933 SBC_SEL_OSC_CLK_20MHZ,
2934 SBC_SEL_OSC_CLK_10MHZ
2952 SBC_VS_UV_NOEVENT = 0x00U,
2958 SBC_VS_OV_NOEVENT = 0x00U,
2964 SBC_VCC1_OV_NOEVENT = 0x00U,
2970 SBC_VCC1_UV_PREWARN_NOEVENT = 0x00U,
2971 SBC_VCC1_UV_PREWARN_EVENT
2979 SBC_POR_NOEVENT = 0x00U,
2985 SBC_VCC2_OT_NOEVENT = 0x00U,
2991 SBC_VCC2_UV_NOEVENT = 0x00U,
2997 SBC_VCC1_SC_NOEVENT = 0x00U,
2998 SBC_VCC1_SC_TO_GND_EVENT
3003 SBC_VCC1_UV_NOEVENT = 0x00U,
3012 SBC_TSD2_SAFE_NOSAFESTATE = 0x00U,
3013 SBC_TSD2_SAFE_SAFESTATE_DETECTED
3018 SBC_TSD2_NOEVENT = 0x00U,
3024 SBC_TSD1_NOEVENT = 0x00U,
3030 SBC_TPW_NOEVENT = 0x00U,
3039 SBC_DEV_STAT_CLEARED = 0x00U,
3040 SBC_DEV_STAT_RESTART_AFTER_FAIL,
3041 SBC_DEV_STAT_SLEEP_MODE
3046 SBC_WD_FAIL_NOFAIL = 0x00U,
3053 SBC_SPI_FAIL_NOEVENT = 0x00U,
3059 SBC_FAILURE_NOEVENT = 0x00U,
3068 SBC_CANTO_NORMAL = 0x00U,
3074 SBC_SYSERR_NOEVENT = 0x00U,
3080 SBC_CAN_FAIL_NO_FAIL = 0x00U,
3082 SBC_CAN_FAIL_TXD_DOM_TO,
3083 SBC_CAN_FAIL_BUS_DOM_TO
3088 SBC_VCAN_UV_NOEVENT = 0x00U,
3097 SBC_CAN_WU_NOEVENT = 0x00U,
3103 SBC_TIMER_WU_NOEVENT = 0x00U,
3109 SBC_WK_WU_NOEVENT = 0x00U,
3118 SBC_GPIO_WK_WU_NOEVENT = 0x00U,
3119 SBC_GPIO_WK_WU_EVENT
3127 SBC_DEV_LVL_NORMAL = 0x00U,
3128 SBC_DEV_LVL_DEVELOPMENT_MODE
3133 SBC_CFG0_STATE_CONFIG_2_4 = 0x00U,
3134 SBC_CFG0_STATE_CONFIG_1_3
3139 SBC_GPIO_LVL_LOW = 0x00U,
3145 SBC_WK_LVL_LOW = 0x00U,
3154 SBC_GPIO_OC_NOEVENT = 0x00U,
3163 SBC_GPIO_OL_NOEVENT = 0x00U,
3182 SBC_SYNC_NOT_SYNCHRONOUS = 0x00U,
3183 SBC_SYNC_VALID_FRAME_RECEIVED
3188 SBC_CANSIL_NOT_EXCEEDED = 0x00U,
3194 SBC_SWK_SET_SWK_NOT_ACTIVE = 0x00U,
3195 SBC_SWK_SET_SWK_ACTIVE
3200 SBC_WUP_NO_WUP = 0x00U,
3206 SBC_WUF_NO_WUF = 0x00U,
3215 SBC_ECNT_NOEVENT = 0x00U,
3216 SBC_ECNT_31_FRAME_ERRORS = 0x1FU,
3217 SBC_ECNT_ERROR_OVERFLOW = 0x20U
3231 SBC_FAM_DRIVER = 0x01U,
3236 SBC_FAM_MIDRANGEPLUS = 0x07U
3241 SBC_PROD_TLE9461 = 0x06U,
3242 SBC_PROD_TLE9461V33,
3243 SBC_PROD_TLE9471 = 0x0EU,